//***************************************************************************
//   Copyright(c)2020, Xidian University D405.
//   All rights reserved
//
//   IP Name         :   Null
//   File name       :   cr_slow_to_fast.v
//   Module name     :   cr_slow_to_fast
//   Author          :   Wang Zekun
//   Date            :   2022/06/30
//   Version         :   v1.0
//   Verison History :   v1.0/
//   Edited by       :   Wang Zekun
//   Modification history : v1.0 Initial revision
//
// ----------------------------------------------------------------------------
// Version 1.0       Date(2022/06/30)
// Abstract : sync 62.5MHz signal to 312.5MHz
//
//-----------------------------------------------------------------------------
// Programmer's model
//
//-----------------------------------------------------------------------------
//interface list :
//                

module cr_slow_to_fast (
    input  wire                           clk_f_i,
    input  wire                           resetn_f_i,
    input  wire                           signal_s_i,
    output wire                           signal_f_o
  );

  reg [2:0] reg_shift;
  always @(posedge clk_f_i or negedge resetn_f_i) begin
    if(~resetn_f_i) begin
      reg_shift <= 3'b000;
    end
    else begin
      reg_shift <= {reg_shift[1:0],signal_s_i};
    end
  end

  assign signal_f_o = ~reg_shift[2] & reg_shift[1];

endmodule
